A seasoned silicon design leader with deep expertise in High-speed SerDes, analog/mixed-signal design, ADCs and end-to-end chip development. Over two decades of experience spanning startups (Cosmic Circuits) and multinational corporations including Intel, Cadence and Samsung. Proven track record of taking complex IPs from specification through silicon validation to productization. Holds 9 patents (with 4 pending) and has published in IEEE. Master’s from IISc Bangalore. Managed full product lifecycles from pre-sales through architecture, design, and delivery.

Analog and mixed-signal design expert with deep hands-on experience across PLLs, CDRs, High Speed TX & RX, DACs, SAR ADCs, LDOs and Bandgaps. Led the design of Ultra-Low Jitter and advanced clocking architectures including LC/RO PLLs, fractional/integer/SSC PLLs, PI/SDM, and injection-locked loops. Holds 8 US patents (2 pending) and has 3 IEEE publications.